Methods for automatic speedup of OpenCL and CUDA code
Research Group Scientific Computing, University of Vienna
High Performance Computing research programe deals with the low level optimization of computational patters, focusing specifically on efficient use of high performance accelerators. Nowadays computing systems expose high degree of parallelism by using multiple computing nodes with multi-core processors and heterogeneity by using accelerators, such as GPUs or Intel MIC. Despite intensive research in compilers, domain specific frameworks and autotuning tools, it is still very challenging to exploit computational power of highly parallel heterogeneous systems – one has to deal both with a distribution of the workload over multiple computing nodes (so-called inter-node parallelism) as well as with the distribution of the particular tasks (workload parts) over multiple cores of each computing node (so-called intra-node parallelism).
The research in this programme will follow two tightly-coupled directions:
(1) research of simplified, efficient and performance-portable programming of parallel multi- and many-core processors, and
(2) research of efficient inter- and intra-node parallelization using task management systems.
The main aims of this research subprogramme include simplifying the programming of parallel processors (conventional CPUs and accelerators) by automatization of some optimization methods, and thus enabling developers to write performance-portable code by using automatic tools allowing the code to adapt to a given architecture. Moreover, we also plan to understand parallel patterns for task management systems and their efficient implementation in software, as well as improving efficiency of using various OpenCL devices with such task management systems by extending their current implementation.
Our research efforts will lead to preparation of scientific papers and software tools, deployed on the CERIT-SC infrastructure and made available to HPC community world-wide. Moreover, the extended internal knowledge of architecture-aware optimization, autotuning and task management systems will improve ability of our group to assist CERIT-SC partners with adaptation of their codes to the provided infrastructure, thus improving its efficient use.
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